The present invention relates to a semiconductor memory device, and, more particularly, to a semiconductor memory device for providing highspeed address access and highspeed data access.
For achieving high-speed operation in a semiconductor memory device, a synchronous dynamic random access memory (SDRAM) has been developed. The SDRAM operates in synchronization with an external clock signal. The SDRAM includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM, and the like.
Referring to FIG. 1, the conventional semiconductor memory device includes a clock buffer and generator 100, a control/address block 110 having a control signal buffer 111 and an address buffer 112, and a command decoder 120. The clock buffer and generator 100 receives an external clock EXT_CLK to generate an internal clock INT_CLK, which is inputted into the control signal buffer 111 and into the address buffer 112. The control signal buffer 111 receives a control signal CNTL to generate a buffered control signal BUF_CNTL in synchronization with the internal clock INT_CLK. The command decoder 120 decodes the buffered control signal BUF_CNTL to output a command signal CMD. In the same manner, the address buffer 112 receives an address signal ADDR to generate a buffered address signal BUF_ADDR in synchronization with the internal clock INT_CLK.
As shown in FIG. 2, the skew between the external clock EXT_CLK and the internal clock INT_CLK is about 1.5 nanoseconds. That is, the rising edge of the internal clock INT_CLK is generated 1.5 nanoseconds following the rising edge of the external clock EXT_CLK. This causes the command signal CMD to also have a time delay corresponding to the skew. As a result, both the address access time (tAA) and the data access time (tAC)of the semiconductor memory device are reduced.
In accordance with an aspect of the invention, there is provided a semiconductor memory device comprising: a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in substantial synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in substantial synchronization with the DLL clock; and an address or CAS buffer for receiving and buffering an external address or CAS signal to generate an internal address or CAS signal in substantial synchronization with the DLL clock.
In accordance with another aspect of the invention, there is provided a semiconductor memory device comprising: a clock control unit for receiving a delay locked loop (DLL) disable signal, a DLL reset signal, a power-up signal, a self-refresh request signal and a self-refresh signal to generate a DLL control signal and a clock selection signal; a clock generation unit for receiving an external clock and the power-up signal to generate an internal clock; a DLL clock buffer unit for generating a DLL clock using the external clock; a column address strobe (CAS) buffer unit for receiving and buffering the DLL control signal, an external CAS signal and a reference voltage signal to generate an internal CAS signal and an inverted internal CAS signal; and a CAS latch unit for receiving and latching the internal CAS signal, the inverted internal CAS signal, the internal clock, the DLL clock, the DLL control signal, the external CAS signal and the reference voltage signal to generate a final CAS signal and an inverted final CAS signal.
In accordance with still another aspect of the invention, there is provided a method of propagating a signal through a semiconductor memory device. The method comprises the steps of: providing an external clock; buffering the external clock; generating a delay locked loop (DLL) clock in substantial synchronization with the external clock; and providing the DLL clock to a control signal buffer and an address buffer.